ZL40205LDG1

The ZL40204 is an LVPECL clock fanout buffer with six output clock drivers capable of operating at frequencies up to 750MHz.

Inputs to the ZL40204 are externally terminated to allow use of precision termination components and to allow full flexibility of input termination. The ZL40204 can accept DC coupled LVPECL or LVDS and AC coupled LVPECL, LVDS, CML or HCSL input signals; single ended input signals can also be accepted. A pin compatible device with internal termination is also available.

The ZL40204 is designed to fan out low-jitter reference clocks for wired or optical communications applications while adding minimal jitter to the clock signal. An internal linear power supply regulator and bulk capacitors minimize additive jitter due to power supply noise. The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature range -40°C to +85°C.

Key Features

• Ultra low additive jitter of 36 fs RMS
• Accepts differential or single-ended input: LVPECL, LVDS, CML, HCSL, LVCMOS
• On-chip input termination resistors and biasing for AC coupled inputs
• Six precision LVPECL outputs, Operating frequency up to 750 MHz
• Options for 2.5 V or 3.3 V power supply with core current consumption of 110 mA
• On-chip Low Drop Out (LDO) Regulator for superior power supply rejection