V62/07649-01XA

The C64x+™ DSPs, such as the SM320C6455-EP device, represent the pinnacle of fixed-point DSP technology within the C6000™ DSP platform. With its advanced VelociTI™ VLIW architecture and 90-nm process technology, the C6455 device delivers unparalleled performance of up to 9600 million instructions per second (MIPS) at a clock rate of 1.2 GHz. This makes it a cost-effective solution for high-performance DSP programming challenges in a variety of applications, including video and telecom infrastructure, imaging/medical, and wireless infrastructure. The device features an impressive eight functional units, integrated Serial RapidIO, and a large on-chip memory system, providing operational flexibility and high-speed data processing capabilities

Key Features

• Controlled Baseline
  • One Assembly Site
  • Test Site
  • One Fabrication Site
• Enhanced Diminishing Manufacturing Sources (DMS) Support
• Enhanced Product-Change Notification
• Qualification Pedigree⁽¹⁾
• High-Performance Fixed-Point DSP (C6455)
  • 1.39 ns, 1.17 ns, 1 ns, and 0.83 ns Instruction Cycle Time
  • 1 GHz Clock Rate
  • Eight 32 Bit Instructions/Cycle
  • 9600 MIPS/MMACS (16 Bits)
  • Commercial Temperature (0°C to 90°C)
  • Extended Temperature (-40°C to 105°C)
  • S-Temp (-55°C to 105°C)
• C64x+™ DSP Core
  • Dedicated SPLOOP Instruction
  • Compact Instructions (16 Bit)
  • Instruction Set Enhancements
  • Exception Handling
• C64x+ Megamodule L1/L2 Memory Architecture:
  • 256K Bit (32K Byte) L1P Program Cache Direct Mapped)
  • 256K Bit (32K Byte) L1D Data Cache 2-Way Set-Associative]
  • 16M Bit (2096K Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation)
  • 256K Bit (32K Byte) L2 ROM
  • Time Stamp Counter
• Enhanced VCP2
  • Supports Over 694 7.95 Kbps AMR
  • Programmable Code Parameters
• Enhanced Turbo Decoder Coprocessor (TCP2)
  • Supports up to Eight 2 Mbps 3GPP (6 Iterations)
  • Programmable Turbo Code and Decoding Parameters
• Endianess: Little Endian, Big Endian
• 64 Bit External Memory Interface (EMIFA)
  • Glueless Interface to Asynchronous Memories (SRAM, Flash, and EEPROM) and Synchronous Memories (SBSRAM, ZBT SRAM)
  • Supports Interface to Standard Sync Devices and Custom Logic (FPGA, CPLD, ASICs, etc.)
  • 32M Byte Total Addressable External Memory Space
• Four 1x Serial RapidIO® Links (or One 4x), v1.2 Compliant
  • 1.25/2.5/3.125 Gbps Link Rates
  • Message Passing, DirectIO Support, Error Management Extensions, and Congestion Control
  • IEEE 1149.6 Compliant I/Os
• DDR2 Memory Controller
  • Interfaces to DDR2-533 SDRAM
  • 32 Bit/16 Bit, 533 MHz (data rate) Bus
  • 512M Byte Total Addressable External Memory Space
• EDMA3 Controller (64 Independent Channels)
• 32/16 Bit Host-Port Interface (HPI)
• 32 Bit 33/66 MHz, 3.3 V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Local Bus Specification version 2.3)
• One InterIntegrated Circuit (I²C) Bus
• Two McBSPs
• 10/100/1000 Mb/s Ethernet MAC (EMAC)
  • IEEE 802.3 Compliant
  • Supports Multiple Media Independent Interfaces (MII, GMII, RMII, and RGMII)
  • Eight Independent Transmit (TX) and Eight Independent Receive (RX) Channels
• Two 64 Bit General-Purpose Timers, Configurable as Four 32 Bit Timers
• UTOPIA
  • UTOPIA Level 2 Slave ATM Controller
  • 8 Bit Transmit and Receive Operations up to 50 MHz per Direction
  • User-Defined Cell Format up to 64 Bytes
• 16 General-Purpose I/O (GPIO) Pins
• System PLL and PLL Controller
• Secondary PLL and PLL Controller, Dedicated to EMAC and DDR2 Memory Controller
• Advanced Event Triggering (AET) Compatible
• Trace-Enabled Device
• IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
• 697-Pin Ball Grid Array (BGA) Package ZTZ or GTZ Suffix), 0.8 mm Ball Pitch
• 0.09 µm/7-Level Cu Metal Process (CMOS)
• 3.3/1.8/1.5/1.25/1.2 V I/Os, 1.25/1.2 V Internal

⁽¹⁾Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

C64x+, JTAG, C64x+, VelociTI, C6000, Code Composer Studio, DSP/BIOS, XDS are trademarks of Texas Instruments.