SSD1961G40

Key Features

• Integrated Display Memory
• Embedded 80K byte SRAM display memory.
• CPU Interface
• Direct support of the following interfaces:
• Motorola MC68K.
• MPU bus interface using WAIT# signal.
• Direct memory mapping of internal registers into upper 128 bytes of 128K byte address space.
• The 80K byte display memory is directly and contiguously available through the 17-bit address bus.
• Display Support
• 9/12 bits Active Matrix TFT interface
• Example resolutions: 160x160, 320x240
• Display Modes
• 8 bit-per-pixel, 256-level color display.
• 256 simultaneous of 4096 colors on active matrix LCD panels.
• Virtual display support (displays images larger than the panel size through the use of panning and scrolling).
• Split screen display allows two different images to be simultaneously displayed.
• Fixed Window Mode simplifies the data update process for an image in a window area on the display.
• Floating Window Mode allows to display an image in a window area on the display without erasing the original image data.
• Clock Source
• Maximum input clock (CLKI) frequency of 50MHz.
• Maximum operating clock (CLK) frequency of 25MHz.
• Operating clock (CLK) is derived from CLKI or BCLK input.
• Pixel Clock (PCLK) and Memory Clock (MCLK) are derived from CLK.
• Miscellaneous
• Software Color Invert.
• Software Power Saving mode.
• Hardware Power Saving mode.
• LCD power-down sequencing.
• 4 General Purpose Input/Output pins are available.
• GPIO0 is available if Hardware Power Saving is not required.
• GPIO[4:2] are available if 9 bit TFT panel is selected.
• Single Supply : 3.0 volts to 3.6 volts.