HMC7043LP7FE

The HMC7043 is designed to meet the requirements of multicarrier GSM and LTE base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs.

Key Features

• JEDEC JESD204B/JESD204C support
• Low additive jitter: <15 fs rms at 2457.6 MHz (12 kHz to 20 MHz)
• Very low noise floor: −155.2 dBc/Hz at 983.04 MHz
• Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs)
  
  • Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx frequency of 3200 MHz
  • JESD204B/JESD204C-compatible system reference (SYSREF) pulses
  • 25 ps analog and ½ clock input cycle digital delay independently programmable on each of 14 clock output channels
• SPI-programmable adjustable noise floor vs. power consumption
• SYSREF valid interrupt to simplify JESD204B/JESD204C synchronization
• Supports deterministic synchronization of multiple HMC7043 devices
• RFSYNC pin or SPI-controlled SYNC trigger for output synchronization of JESD204B/JESD204C
• GPIO alarm/status indicator to determine the health of the system
• Clock input to support up to 6 GHz
• On-board regulator for excellent PSRR
• 48-lead, 7 mm × 7 mm LFCSP package

Application

• JESD204B/JESD204C clock generation
• Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)
• Data converter clocking
• Phase array reference distribution
• Microwave baseband cards