DS90CR288AMTDX/NOPB
LVDS Interface IC +3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link Receiver - 85 MHz 56-TSSOP -10 to 70
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Part Number : DS90CR288AMTDX/NOPB
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Package/Case : 56-TSSOP
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Brands : TI
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Components Categories : Specialized
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Datesheet : DS90CR288AMTDX/NOPB DataSheet (PDF)
Overview of DS90CR288AMTDX/NOPB
The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted.
The DS90CR288A receiver converts the four LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 85 MHz, 28 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 2.38 Gbit/s (297.5 Mbytes/sec).
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
Key Features
- 20 to 85 MHz Shift Clock Support
- 50% Duty Cycle on Receiver Output Clock
- 2.5 / 0 ns Set & Hold Times on TxINPUTs
- Low Power Consumption
- ±1V Common-Mode Range (around +1.2V)
- Narrow Bus Reduces Cable Size and Cost
- Up to 2.38 Gbps Throughput
- Up to 297.5 Mbytes/sec Bandwidth
- 345 mV (typ) Swing LVDS Devices for Low EMI
- PLL Requires no External Components
- Rising Edge Data Strobe
- Compatible with TIA/EIA-644 LVDS Standard
- Low Profile 56-Lead TSSOP Package
Specifications
The followings are basic parameters of the part selected concerning the characteristics of the part and categories it belongs to.
Source Content uid | DS90CR288AMTDX/NOPB | Pbfree Code | Yes |
Rohs Code | Yes | Part Life Cycle Code | Active |
Ihs Manufacturer | TEXAS INSTRUMENTS INC | Part Package Code | TSSOP |
Package Description | TSSOP, TSSOP56,.3,20 | Pin Count | 56 |
Reach Compliance Code | compliant | ECCN Code | EAR99 |
HTS Code | 8542.39.00.01 | Samacsys Manufacturer | Texas Instruments |
Differential Output | YES | Input Characteristics | DIFFERENTIAL |
Interface IC Type | LINE RECEIVER | Interface Standard | EIA-644; TIA-644 |
JESD-30 Code | R-PDSO-G56 | JESD-609 Code | e3 |
Length | 14 mm | Moisture Sensitivity Level | 2 |
Number of Functions | 1 | Number of Terminals | 56 |
Operating Temperature-Max | 70 °C | Operating Temperature-Min | -10 °C |
Package Body Material | PLASTIC/EPOXY | Package Code | TSSOP |
Package Equivalence Code | TSSOP56,.3,20 | Package Shape | RECTANGULAR |
Package Style | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH | Peak Reflow Temperature (Cel) | 260 |
Power Supplies | 3.3 V | Qualification Status | Not Qualified |
Receive Delay-Max | 3.5 ns | Receiver Number of Bits | 4 |
Seated Height-Max | 1.2 mm | Supply Current-Max | 135 mA |
Supply Voltage-Max | 3.6 V | Supply Voltage-Min | 3 V |
Supply Voltage-Nom | 3.3 V | Supply Voltage1-Max | 3.6 V |
Supply Voltage1-Min | 3 V | Supply Voltage1-Nom | 3.3 V |
Surface Mount | YES | Technology | CMOS |
Temperature Grade | COMMERCIAL | Terminal Finish | MATTE TIN |
Terminal Form | GULL WING | Terminal Pitch | 0.5 mm |
Terminal Position | DUAL | Time@Peak Reflow Temperature-Max (s) | 30 |
Width | 6.1 mm |
Warranty & Returns
Warranty, Returns, and Additional Information
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QA & Return Policy
Parts Quality Guarantee: 365 days
Returns for refund: within 90 days
Returns for Exchange: within 90 days
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Parts Packaging Guarantee: Featuring 100% ESD anti-static protection, our packaging incorporates high toughness and superior buffering capabilities.
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