87016AYLF

Divide select inputs, DIV_SELA:DIV_SELD, provide precise control over the output frequency of each bank, while the bank enable inputs, CLK_ENA:CLK_END, allow for individual bank enabling and disabling. The circuitry also includes a synchronizer to prevent runt pulses when enabling or disabling the clock outputs, adding another layer of reliability to its performance. Additionally, the master reset input, nMR/OE, resets the ÷1/÷2 flip flops and controls the active and high impedance states of all outputs

Key Features

• Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs)
• Selectable differential CLK1, nCLK1 or LVCMOS clock input
• CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• CLK0 supports the following input types: LVCMOS, LVTTL
• Maximum output frequency: 250MHz
• Independent bank control for ÷1 or ÷2 operation
• Independent output bank voltage settings for 3.3V, 2.5V, or 1.8V operation
• Asynchronous clock enable/disable
• Output skew: 170ps (maximum)
• Bank skew: 30ps (maximum)
• Part-to-part skew: 750ps (maximum)
• 3.3V core, 3.3V, 2.5V, or 1.8V output operating supply
• 0°C to 85°C ambient operating temperature
• Available in lead-free RoHS compliant package